The present disclosure relates to data transfer devices and wireless communication circuits. Between a microcontroller and its peripheral devices, serial data is transmitted and received using an eight-bit data as a unit. As one of such serial data transfer techniques, for example, a bus protocol referred to as I2C bus is well known. In the I2C bus protocol, data transfer is performed using a bidirectional two-wire bus consisting of a serial clock line and a serial data line. A plurality of data transfer devices can be connected to the I2C bus. Each data transfer device functions as a master device having control authority of a data transfer or as a slave device performing a data transfer in response to a request from the master device. A serial clock signal is supplied from the master device to each of the slave devices through the serial clock line. Each slave device operates in synchronization with the serial clock signal. In the I2C bus protocol, the serial clock signal is also supplied to the slave device that does not receive a process request from the master device. In view of such matters in the background, Japanese Unexamined Patent Application Publication No. 2008-293230 proposes to stop transferring the serial clock signal from the master device to its own device when it is determined that the process request from the master device is not addressed to its own device.